As is well known by those skilled in the art, a continuing goal in manufacturing and production of semiconductors is a reduction in size of components and circuits with the concurrent result of an increase in the number of circuits and/or circuit elements such as transistors, capacitors, etc., on a single semiconductor device. This relentless and successful reduction in size of the circuit elements has also required reduction in the size of the conductive lines connecting devices and circuits. However, as the conducting lines are designed to be smaller and smaller, the resistance of the interconnects increases. Further, as the number of dielectric layers increases, the capacitive coupling between lines on the same level and adjacent level increases.
In the past, aluminum was used as the metal interconnect lines and silicon oxide as the dielectric. However, newer manufacturing techniques now favor copper as the metal for interconnect lines and various low K materials (organic and inorganic) are favored as the dielectric material. Not surprisingly, these material changes have required changes in the processing methods. In particular, because of the difficulty of etching copper without also causing unacceptable damage to the dielectric material, the technique of forming the metal interconnect lines has experienced significant changes. Namely, whereas aluminum interconnects could be formed by depositing a layer of aluminum and then using photoresist, lithography, and etching to leave a desired pattern of aluminum lines, the formation of copper interconnect lines are typically formed by a process now commonly referred to as a Damascene process. The Damascene process is almost the reverse of etching, and simply stated a trench, canal or via is cut, etched or otherwise formed in the underlying dielectric and is then filled with metal (i.e., copper).
The process is rather straightforward if the metallization or copper layer was to be formed at only one level. However, as is well known by those skilled in the art, semiconductor devices are now formed at multiple levels on a chip and consequently metallization or interconnects, which are on the order of 100 nm (nanometers) and less, must also be formed at each level. Further, not only are multiple levels of metallization required, but these multiple levels must be interconnected. The possibility of difficulty in achieving the necessary registration of 100 nm connecting vias through the dielectric (which will then be filled with copper) that will align with a 100 nm interconnect line at another level in the same semiconductor device becomes apparent.
To facilitate alignment and registration, one approach has been the use of titanium nitride, TiN, as a metal hardmask for etching the trenches and inter-level connecting vias. The TiN is sufficiently translucent to wavelengths of light used by the lithography process such that alignment does not pose a difficult problem. Unfortunately, because of the presence of oxygen during an RIE (reactive ion etch) process used to cut the vias, the titanium in the metal compound leaves a TiOx based residue on the etched surfaces. The TiOx can increase capacitance and affect the reliability and yield of the process.
It is also been found that the use of TaN as a metal hardmask does not result in the formation of metal oxide residue such as occurs when TiN is used. However, TaN doesn't have the translucent characteristics of TiN and presents problems in aligning the template pattern with lower metal levels, especially aligning level M3 with level M4.
Therefore, a metal hardmask having satisfactory translucent characteristics to avoid alignment problems and that did not leave a metal oxide residue on the etched surface would be advantageous.